Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment is routinely used to produce devices having geometries as small as 28 nm and less, and new equipment designs are continually being developed and implemented to produce devices with even smaller geometries. As device geometries decrease, the impact of interconnect capacitance on device performance increases. To reduce interconnect capacitance, inter-layer materials that have traditionally been formed of silicon oxide are being formed using lower dielectric constant materials (low k materials). Some low k materials that have been used include fluorinated silicon oxide, carbonated silicon oxide, and various polymers and aerogels. While these and other low k materials have been used successfully in the manufacture many different types of integrated circuits, new and improved processes that can create regions of low dielectric constant material between adjacent metal lines on substrates are desirable.
Copper lines are desirable because of their low resistivity. Using copper lines decreases signal loss but also raises the maximum frequency of operation for integrated circuits. The signal delay is proportional to the resistance of the copper lines times the capacitance between copper lines. However, it has been difficult to reduce the capacitance of the interlayer insulating layer used with copper interconnects due to process sequence integration issues.
Methods are needed to form gas pockets (generally referred to as air gaps) between low-resistivity metal (e.g. copper) lines in integrated circuits.